Wie stellt sich die Übertragungsrate von PCIe ein?
In der Spezifikation von PCIe ist für jede Lane und jede PCIe-Generation eine maximale Taktfrequenz spezifiziert.
Ist das nur das Maximum und Host und Client handeln jeweils eine individueelle Taktfrequenz aus (Anpassung z.B. an schlechte Leitungsverbinduung)?
Oder arbeiten diese Lanes immer nur mit der einen festen Taktfrequenz (= Maximum) und die geringere Datentransferleistung der eingesteckten Karten wird dann dadurch erzeugt, dass die Daten blockweise übertragen werden mit beliebig langen Pausen dazwischen.
Im letzter Fall muss die HW-mäßige Datenübertragung bei der Maximalfrequenz absolut sicher funktionieren, da sonst nicht weniger Daten (wegen geringerer Frequenz) sondern keine Daten (wegen häufiger Fehler) übertragen werden.
Kennt sich hier jemand aus?
Ambesten mit Links zum Weiterlesen – Danke.
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PCIe is a Standardised Protocol, which means that it is precisely specified how the data transmission is to be implemented and what specifications are used.
Therefore, there are no individual clock rates or any manufacturer-specific adjustments. There must be no different behavior between devices with the same PCIe protocol.
In practice, two devices, e.g. motherboard and graphics card, agree on a PCIe version. Which version is supported can be read on the electronic level. PCIe requires a downward compatibility, a device that supports PCIe 5.0 must also support 4.0, 3.0, 2.0 and 1.0.
If the two devices have agreed to one version, we say, for example, PCIe 4.0, then both devices have to behave exactly as the PCIe-4.0 standard requires. It doesn’t matter if one of the two devices also supports PCIe 5.0, both of them behave like PCIe 4.0 devices at the moment. With regard to data transmission, there must be no difference between a PCIe-5.0 device in PCIe-4.0 mode and a PCIe-4.0 device.
How exactly this works on an electronic level would probably be a very complex issue in which I am not really in it, but from a user point of view it really doesn’t matter. Because this is the ingenious thing about a standard like PCIe – it pretends exactly how the devices have to communicate. Thus, as long as both devices comply with the PCIe standard, a stable and reliable data transmission is ensured, since from the point of view of each device the respective other device behaves exactly as any other PCIe device. Therefore, no additional error correction or any adjustments to the other device are required. All that matters is the PCIe version.
Historically, PCIe has proven to be a very reliable standard, which is of course one of the reasons for being so successful and being used almost everywhere in computers. This shows that the standard specifies the right things and ensures that really every device that correctly implements the standard is the same.
Normally, host and client act with one another a fixed transmission rate corresponding to the common minimum standard according to a predefined protocol.
Accordingly, something between PCIe 1.x to 4 or 5. There’s nothing in between.
So either PCIe 4 or PCIe 5, and no intermediates?
If a weaker component is attached to the controller, then the agreement can also lie with PCIe 3.2 or 1.
The weakest component in the controller client connection determines the maximum applicable protocol on the relevant PCIe controller channel.
I’m out now because it’s going to be a doctoral thesis.
Partly consent, except for one point:
Dsas really only what hisher is really fast in the PC – apart from the CPU itself – this is the RAM. And this is already extremely fast connected to your connection, which is better than PCIe 5.0.
And also with the graphics cards that will work with PCIe 5.0, there are the data packets that are to be moved there and, of course, land in a RAM.
I fully agree with you on all other points.
Therefore, I wonder if the PCIe specification team really thinks reasonable if we are already discussing specifications for PCIe 6.0. Much closer than now, neither graphics card nor SSD memory can be positioned on the CPU.
This is primarily only a question of maximum permissible line lengths and conductor materials in a PCIe point-to-point connection for the signal quality.
For PCIe 4 compared to 3, these line lengths had to be reduced from about 20″ to 8-12″ and for PCIe 5, these parameters, together with improved error correction, will probably again be captured in more compact frame conditions.
But are we honest… what hardware components apart from high-end GPUs and CPU-PCH Point2Point are really going to load PCIe 5, 6 or 7 to 16 or (thinkable) up to 32 lanes (+)?
Classic semiconductor memories for RAM, VRam and SSDs with current technology will not irritate this as quickly as they continue to be very lame internally in relation.
At fast S-Ram, SD cells in their switching speeds do not even get close to them. (See among others S-Ram Caches and their throughput rates in CPUs vs. D-Ram)
Exactly and such problems are getting worse when you double the transmission frequency of the signals (reversal from PCIe 4.0 to PCIe 5.0).
Stability problems are most likely to arise in the MaxOut of the overall architecture given on the platform side, consisting of the transfer type of the lines and line lengths on the motherboard and the quality of the controllers corresponding to one another in the respective protocol.
Can you count on PCIe working hard?
Or can there be transmission errors in recent versions because the hardware is not as good as it should be according to the standard?
On PCIe there are also assignment/and parity bits during data transmission in the protocol. Therefore, in the case of older PCIe standards, only about 70 to 80% of the gross transmission performance was actually exploitable for user data transmissions.
From PCIe 4/5, I don’t know the whole thing (more) because of the lack of interresses. What exactly is your problem?
Thank you.
Is there a measurement of the DAten transmission quality by the host (or the CPU), or does the host rely on a speed parameter that its client communicates to it?
Look at the manual at pci lanes. Cycle rates were declining in the past millennium alone.
What is the manual for PCIe-Lanes?
Look into the UEFi / Bios. I mean your motherboard’s doc.
There’s in which PCIe version supports the motherboard, but there’s no description of how PCIe works.