How is a value stored in an SR latch, D latch and D flip-flop?
It is the case that if I set the SR latch Set to 1 and R to 0, for example, my output Q has the value 1 and stays at 1 all the time because of the feedback, right?
My problem is:
Let's say I have the SR-Catch and I set S=1 and R=0, so Q=1 and !Q=0 see:
What I don't understand is that if I want to have the stored value, I say S=0 and R=0, but how do I set S and R while the circuit is running? If I change the bits, won't that cause problems?
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Ich kann deine Frage nicht ganz nachvollziehen. Was meinst du “während das Schaltwerk läuft” ? Da läuft nicht viel. Auslesen kannst du den Zustand von Q und !Q immer, unabhängig davon, ob S=1 R=0 oder S=0 R=0 anliegt.
Lade dir doch Logisim herunter und probiere das aus:
http://www.cburch.com/logisim/de/download.html
Typically, computers' memories are constructed from multiple DFFs (one per bit of bus width), with a tristate driver behind each memory. The DFF's data inputs are connected to the bus, the outputs go to the tristate driver's input, and the tristate driver's outputs go to the data bus. The processor's logic/control unit determines what happens:
Inactive: "Load" the register inactive, tristate driver inactive
Read data: Switch on the tristate driver (active), then the data from the output of the DFF is on the bus
Write data: switch on "load", then the data is transferred from the data bus to the DFF.